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MYSON TECHNOLOGY
FEATURES
* Total of 33 single word instructions . * The fast execution time may be 200ns for all single cycle instructions under 20MHz operating. * Operating voltage range: 2.3V ~ 6.5V * 8-bit data bus. * 14-bit instruction word. * Four-level stacks. * On chip EPROM size : 512x14 bits for MTU8B54E/55E, 1Kx14 bits for MTU8B56E, 2Kx14 bits for MTU8B57E. * Internal RAM size : 25 bytes for MTU8B54E/56E, 24 bytes for MTU8B55E, * 72 bytes for MTU8B57E. * Direct and indirect addressing modes for data accessing * 8-bit real time clock/counter with 8-bit programmable prescaler. * Internal power-on Reset. * Device Reset Timer. * Code protection. * Sleep mode for power saving. * On chip Watchdog Timer(WDT) based on internal RC oscillator. * Three I/O ports PA, PB nad PC with independent direction control.
MTU8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
* 4 types of oscillator can be selected by code options: - RC : Low-cost RC oscillator - XTAL : Standard crystal oscillator - HFXTAL : High frequency crystal oscillator - LFXTAL : Low frequency crystal oscillator
GENERAL DESCRIPTION
MTU8B5X series is an EPROM based 8-bit microcontroller which employs a full CMOS technology enhanced with low-cost, high speed and high noise immunity. Watchdog Timer, RAM, EPROM, tri-state I/O port, power down mode, and real time programmable clock/counter are integrated into this chip. MTU8B5X contains 33 instructions, all are single cycle except for program branches which take two cycles. On chip memory is available with 512x14 bits of EPROM for MTU8B54E/55E, 1Kx14 bits of EPROM for MTU8B56E, 2Kx14 bits of EPROM for MTU8B57E and 24 to 72 bytes of static RAM.
BLOCK DIAGRAM
Vdd Vss Configuration Word
Osc Mode 2 Select
Four-level Stack
11
Program Counter
11
Enable /Disable
OSCI OSCO MCLR
Sleep
WatchDog Timer Oscillator Circuit
EPROM
512 X 14 TO 2048 X 14 14
Instruction Register T0CKI WDT/Timer0 Prescaler
6 WDT Time Out 14
Timer0
Data
Instruction Decoder
4
T0MODE Register
6
8
RAM
24, 25 or 27 Bytes
PortA
PA3:PA0
Accumulator FSR
PortB
8
PB7:PB0
PortC Status ALU
8
Only in MTU8B55E/57E
8
PC7:PC0
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. Revision 1.2 -1 24 October 2000
MYSON TECHNOLOGY
1.0 PIN CONNECTION
MTU8B54E/55E/56E/57E
T0CKI Vdd PA2 PA3 T0CKI MCLR/Vpp Vss PB0 PB1 PB2 PB3 1 2 3 4 5 MTU8B54E 6 MTU8B56E 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSCI OSCO Vdd PB7 PB6 PB5 PB4
N/C
Vss
N/C
PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4
1 2 3 4 5 6 7 MTU8B55E 8 MTU8B57E 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
MCLR/Vpp OSCI OSCO PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5
2.0 PIN DESCRIPTIONS
Name OSCI
I/O I
Descriptions RC type: Input pin of RC oscillator XTAL type: Input terminal of crystal oscillator RC type: OSCO outputs with 1/4 frequency of OSCI to denotes the cycle rate for instruction. XTAL type: Output terminal of crystal oscillator
OSCO T0CKI/SCL
O I
Input pin of real time counter/clock. Must be tied to Vss or Vdd if not in use. Input pin for device reset or high voltage programming input for EPROM. If this pin is low, the device is reset.
MCLR/Vpp
I
In programmimg mode, this pin is connected to 12V. In normal operating mode, this pin must not exceed Vdd to avoid entering unintended programming mode. PA0~PA3 as bi-directional I/O port PB0~PB7 as bi-directional I/O port PC0~PC7 as bi-directional I/O port Power supply Ground
PA0~PA3 PB0~PB7 PC0~PC7 Vdd Vss
I/O I/O I/O -
Revision 1.2
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MYSON TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTIONS 3.1 REGISTER MAP
MTU8B54E/55E/56E/57E
The register map of MTU8B5X is depicted as below:. The Register Map of MTU8B54E/56E Address 00h 01h 02h 03h 04h 05h 06h 07h-1Fh Description Indirect Addressing Register Timer0 PC STATUS FSR PORTA PORTB General Purpose Register The Register Map of MTU8B55E Address 00h 01h 02h 03h 04h 05h 06h 07h 08h-1Fh The Register Map of MTU8B57E Address FSR<6:5> 00h 01h 02h 03h 04h 05h 06h 07h 08h~0Fh Bank 0 00 Indirect Addressing Register Timer0 PC STATUS FSR PORTA PORTB PORTC General Purpose Register 10h~1Fh General Purpose Register 30h~3Fh General Purpose Register 50h~5Fh General Purpose Register 70h~7Fh General Purpose Register Map back to address in Bank 0 Bank 1 01 Description Bank 2 10 Bank 3 11 Description Indirect Addressing Register Timer0 PC STATUS FSR PORTA PORTB PORTC General Purpose Register
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MTU8B54E/55E/56E/57E
3.1.1 INAR(Indirect Address Register) : R0 R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction accessing this register can access data pointed by FSR(R4). 3.1.2 Timer0(8-bit real-time clock/timer) : R1 This register increases by an external signal edge applied to T0CKI pin, or by internal instruction cycle. It can be read or written as any other register. 3.1.3 PC(Program Counter) : R2 This register increases itself every instruction cycle, except the following condition shown in Figure 1: LCALL, LGOTO : from instruction word RETIA : from STACK
LCALL A10~A0 RETIA FIGURE 1. Program Counter 3.1.4 STATUS(Status Register): The content of R3 is listed in Table 1. TABLE 1. STATUS Register Bit Symbol Carry/borrow bit 0 C ADDWF = 1, a carry occurred = 0, a carry did not occur Half carry/half borrow bit ADDWF = 1, a carry from the 4th low order bit of the result occurred 1 DC = 0, a carry from the 4th low order bit of the result did not occur SUBWF = 1, a borrow from the 4th low order bit of the result did not occur = 0, a borrow from the 4th low order bit of the result occurred Zero bit: 2 Z = 1, the result of a logic operation is zero = 0, the result of a logic operation is not zero Power down flag bit: 3 PD = 1, after power-up or by the CLRWDT instruction = 0, by the SLEEP instruction Time overflow flag bit: 4 5, 6, 7 TO = 1, after power-up or by the CLRWDT or SLEEP instruction = 0, a WDT time-overflow occurred Unused Stack1 Stack2 Stack3 Stack4
Description SUBWF = 1, a borrow did not occur = 0, a borrow occurred
Revision 1.2
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MTU8B54E/55E/56E/57E
3.1.5 FSR(File select register pointer): R4 Bit 0~4 are used to select up to 32 registers (address: 00h~1Fh) and Bit 5~6 are Bank Select (Bank0~3) in the indirect addressing mode shown in Figure 2. 3.1.6 PORT A: R5 PA3:PA0, bi-directional I/O Register 3.1.7 PORT B: R6 PB7:PB0, bi-directional I/O Register 3.1.8 PORT C: R7 PB7:PB0, bi-directional I/O Register, and for MTU8B55E/57E only 3.1.9 T0MODE REGISTER: T0MODE is a write-only register and the content is listed in Table 2. 3.1.10 IOST (Control Port I/O Mode Register) The IOST register is "write-only" = 0, I/O pin in output mode; = 1, I/O pin in input mode. Bank Select Indirect Addressing Mode Location Select
B7
B6
B5
B4
B3
B2
B1
B0
Read 1
70h 50h
Bank 3 Bank 2 30h Bank 1 Bank 0
10h
16 Bytes SRAM 7Fh 5Fh 3Fh 1Fh
00h 01h 02h 03h 04h 05h 06h 07h 08h 0Fh
INAR Timer0 PC STATUS FSR PORT A PORT B PORT C 8 Bytes SRAM Bank 0
FIGURE 2. Data Memory Configuraion
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TABLE 2. T0MODE Register Bit Symbol Bit Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
MTU8B54E/55E/56E/57E
Description Timer Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
2-0
PS2:PS0
Prescaler assign bit: 3 PSC = 0, Timer0 = 1, WDT Timer0 source signal edge select bit: 4 TE = 0, increment when low-to-high transition on T0CKI pin = 1, increment when high-to-low transition on T0CKI pin Timer0 source signal select bit: 5 TS = 0, internal instruction clock cycle = 1, transition on T0CKI pin 6, 7 Unused
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3.2 INSTRUCTION SET Mnemonic Operands
BCR R, bit BSR R, bit BTRSC R, bit
MTU8B54E/55E/56E/57E
Description
Clear bit in R Set bit in R Test bit in R and skip if clear
Cycles
1 1 1 or 2(skip) 1 or 2(skip) 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 or 2(skip)
Instruction Code
11 11bb brrr rrrr 11 10bb brrr rrrr 11 01bb brrr rrrr
Status Affected
None None None
BTRSS R, bit CLRWDT T0MODE SLEEP IOST R ANDIA I XORIA I MOVIA I IORIA I RETIA I LCALL I LGOTO I NOP MOVAR R COMR R, d MOVR R RRR R, d RLR R, d SWAPR R, d CLRA CLRR R INCR R, d INCRSZ R, d
Test bit in R and skip if set Clear Watchdog Timer Load T0MODE Register Go into standby mode Load IOST Register AND immediate with Acc Exclusive OR immediate with Acc Move immediate to Acc Inclusive OR immediate with Acc Return, place immediate in A Call subroutine Unconditional branch No operation Move Acc to R Complement R Move R Rotate right R Rotate left R Swap halves R Clear Acc Clear R Increment R Increment R, Skip if 0
11 00bb brrr rrrr 01 0000 0000 0001 01 0000 0000 0010 01 0000 0000 0011 01 0000 0000 0rrr 00 1001 iiii iiii 00 1000 iiii iiii 00 0001 iiii iiii 00 0011 iiii iiii 00 1100 iiii iiii 10 0iii iiii iiii 10 1iii iiii iiii 01 0000 0000 0000 01 0000 1rrr rrrr 01 0010 drrr rrrr 01 0011 drrr rrrr 01 1110 drrr rrrr 01 1100 drrr rrrr 01 1101 drrr rrrr 01 0001 0000 0000 01 0001 1rrr rrrr 01 1000 drrr rrrr 01 1001 drrr rrrr
None TO, PD None TO, PD None Z Z None Z None None None None None Z Z C C None Z Z Z None
Revision 1.2
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MYSON TECHNOLOGY
Mnemonic Operands
DECR R, d
MTU8B54E/55E/56E/57E
Description
Decrement R
Cycles
1 1 or 2(skip) 1 1 1 1
Instruction Code
Status Affected
01 0110 drrr rrrr Z 01 0111 drrr rrrr None 01 1010 drrr rrrr C, DC, Z 01 1011 drrr rrrr Z 01 0100 drrr rrrr Z 01 0101 drrr rrrr C, DC, Z
DECRSZ R, d Decrement R, Skip if 0 SUBAR R, d XORAR R, d ANDAR R, d ADDAR R, d Subtract Acc from R Exclusive OR Acc with R AND Acc with R Add Acc and R
IORAR R, d Inclusive OR Acc with R 1 01 1111 drrr rrrr Z Note: b : Bit position WDT : Watchdog Timer R : Register address i : Immediate data Acc : Accumulator T0MODE : T0MODE register PD : Power down flag TO : Time overflow bit IOST : I/O port status register Z : Zero flag C : Carry flag DC : Digital carry flag I : (i7i6i5i4i3i2i1i0) R : (r6r5r4r3r2r1r0) d [ 0, 1 ] :Destination If d is "0", the result is stored in the Acc register. If d is "1", the result is stored back in register R.
3.3 I/O PORTS EQUIVALENT CIRCUIT
Acc Data
D Q VDD
IOST Latch IOST R
CK QB
I/O Pin
Data Bus
D
QB
Data Latch WR Port
CK Q
VSS
RD Port Note : 1. The IOST registers are "write-only" and set upon RESET. 2. If the IOST latch is "0", the corresponding I/O pin is in output mode; if the IOST latch is "1", the corresponding I/O pin is in input mode.
Revision 1.2 -824 October 2000
MYSON TECHNOLOGY
3.4 RESET
MTU8B54E/55E/56E/57E
This device may be reset by one of the following ways: (1) Power-on Reset : At power-up, this device will be kept in a RESET condition for a period of 18ms after the voltage on MCLR/Vpp pin has reached a logic high level. (2) MCLR reset (normal operation). (3) WDT reset (normal operation). (4) MCLR wake-up (from sleep mode). (5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device entering into sleep mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This device can be awakened by WDT time-out or reset input on MCLR pin. The contents of registers after reset are listed below: Address 00h 01h 02h 03h 04h 05h 06h 07h 07h-1Fh N/A N/A N/A INAR Timer0 PC STATUS FSR PORTA PORTB PORTC General Purpose Register Acc IOST T0MODE Register Power-On Reset xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 1xxx xxxx ---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 --11 1111 /MCLR or WDT Reset uuuu uuuu uuuu uuuu 1111 1111 000# #uuu 1uuu uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 --11 1111
Note: x = unknown, u = unchanged, - = unimplemented, read as "0", # = refer to the following table
Condition /MCLR Reset (not during SLEEP) /MCLR Reset during SLEEP WDT Reset (not during SLEEP) WDT Reset during SLEEP
Status:bit 4 u 1 0 0
Status:bit 3 u 0 1 0
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MYSON TECHNOLOGY
T0CKI TE FOSC/4 1 0 M U X 1 TS PSC MUX 0
MTU8B54E/55E/56E/57E
3.5 REAL TIME CLOCK (TIMER0) AND WATCHDOG TIMER
WDT enable
WDT 0 PSC MUX 1
Sync 2 cycles
8-bit prescaler
8 bits
Timer0
8 bits
PS2:PS0
8-to-1 MUX
Data Bus PSC
1 MUX
0
WDT Time-Out 3.5.1 Timer0 Timer0 is an 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external clock source presented at the T0CKI pin. To select the internal clock source, bit 5 of the T0MODE register should be reset. In this mode, Timer0 will increase by 1 in every instruction cycle (without prescaler). To select the external clock source, bit 5 of the T0MODE register should be set. In this mode, Timer0 will increase by 1 on every falling or rising edge of T0CKI pin is controlled by bit 4 of T0MODE register. 3.5.2 Watchdog Timer(WDT) The Watchdog Timer is a free running on-chip RC oscillator. This RC oscillator is separated from the RC oscillator of the OSCI pin. That means the WDT will keep running even when the oscillator driver is turned off, such as in sleep mode. During normal operation or in sleep mode, a WDT time-out will cause the device reset and the TO bit (bit 4 of STATUS register) will be cleared. Without prescaler, the WDT time-out period is 18ms. This period can be increased by using the prescaler. The division ratio of prescaler is up to 1:128. Thus, the longest time-out period is approximately 2.3s. 3.5.3 Prescaler The 8-bit prescaler may be assigned to either the Timer0 or the WDT through the PSC bit (bit 3 of the T0MODE register). Setting this bit assigns the prescaler to the WDT. Resetting this bit assigns the prescaler to the Timer0. The PS2:PS0 bits determine the prescale ratio. When assigned to Timer0, the prescaler will be cleared by instructions which write to Timer0 Register. A CLRWDT instruction will clear the WDT and prescaler when assigned to WDT. The prescaler can not be assigned to both the Timer0 and WDT simultaneously.
Revision 1.2
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MYSON TECHNOLOGY
3.6 OSCILLATOR CONFIGURATION
MTU8B54E/55E/56E/57E
This device supports four oscillator modes. Users can program two configuration bits to select the appropriate mode. These oscillator modes offered as: * RC: Low-cost crystal * XTAL: Standard crystal oscillator * HFXTAL: High frequency crystal oscillator * LFXTAL: Low frequency crystal oscillator 3.6.1 XTAL, HFXTAL or LFXTAL modes MTU8B54E/55E/56E/57E Internal Circuit MTU8B54E/55E/56E/57E SLEEP
OSCI RF XTAL C1
OSCO RS
OSCI
OSCO
C2
Open Clock from external system
(a) Crystal Operation (or Ceramic Resonator) 3.6.2 RC Oscillator Mode R OSCI C
0/4
(b) External Clock Input Operation
MTU8B54E/55E/56E/57E internal clock
OSCO
3.7 CONFIGURATION WORD
Bit 3 Bit2 Bit1 Bit0 Code Protect WDT Enable Oscillator Type Oscillator Type 1 x x x 0 x x x x 1 x x x 0 x x x x 1 1 x x 1 0 x x 0 1 x x 0 0 Function EPROM unprotected EPROM protected Watchdog Timer enable Watchdog Timer disable RC HFXTAL XTAL LFXTAL Remark Default Default Default
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4.0 ABSOLUTE MAXIMUM RATINGS
Ambient Operating Temperature Store Temperature DC Supply Voltage(Vdd) Voltage with respect to Ground(Vss) Voltage on MCLR(Vpp) with respect to Ground(Vss)
MTU8B54E/55E/56E/57E
-55oC to +125oC -65oC to +150oC 0V to +7.5V 0.6V to (Vdd + 0.6)V 0V to +12V
5.0 OPERATING CONDITIONS
DC Supply Voltage Operaing Temprature +2.3V to +6.5V -40oC to +85oC
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions) 6.1 ELECTRICAL CHARACTERISTICS of MTU8B54E/56E
Parameter Input High Voltage Input Low Volatge Output Voltage Sleep Current Sym VIH VIL VOh VOL IPD IPD 3.0 <1 8.07 IDD 5.16 3.98 2.05 2.8 1.77 Operating Current IDD 1.31 604 224 88 6.21 IDD 3.91 2.71 1.39 685
Revision 1.2
Min.
Typ. 2.2 4.2 1.1 1.0
Max.
Units Conditions I/O ports, Vdd=5V V MCLR, Vdd=5V V V V V I/O ports, Vdd=5V MCLR, Vdd=5V I/O Ports, Vdd=4.5V, Ioh=-5.4mA, Iol=8.7mA in RC mode WDT Enable, Vdd=3.0V WDT Disable, Vdd=3.0V HFXTAL: 24MHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0v LFXTAL: 32kHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0V Vdd=2.4V Vdd=2.1V ** XTAL: 12MHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0V Vdd=2.4V
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3.8 0.6
V uA uA mA mA mA mA mA mA mA uA uA uA mA mA mA mA uA
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Parameter Sym Min. Typ. 5.01 3.03 IDD 2.05 916 391 195
MTU8B54E/55E/56E/57E
Typ.
Units mA mA mA uA uA uA
Conditions XTAL: 4MHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0V Vdd=2.1V ** Vdd=5V, RC mode, WDT Disable, These values include current through Rext
6.32 3.11 2.46 1.88 1.80 1.73 6.18 2.91 Operating Current 2.31 1.84 1.77 IDD 1.72 5.72 2.60 2.13 1.79 1.75 1.71 5.32 2.45 2.06 1.78 1.74 1.71 ** Operating at Vdd=2.1V is for reference only.
mA mA mA C=3P mA mA mA mA mA mA C=20P mA mA mA mA mA mA mA mA mA mA mA mA C=301P mA mA mA C=101P
R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm
F=7.80MHz F=4.10MHz F=2.38MHz F=617kHz F=311kHz F=103Hz F=6.76MHz F=2.98MHz F=1.67MHz F=403kHz F=202kHz F=65.8kHz F=4.17MHz F=1.33MHz F=676kHz F=154kHz F=75.8kHz F=24.5kHz F=2.34MHz F=617kHz F=313kHz F=64.9kHz F=32.5kHz F=10.4kHz
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Parameter Input High Voltage Sym VIH VIL VOh VOL IPD IPD 3.0 <1 8.87 IDD 5.84 4.09 1.88 2.83 1.96 IDD 1.42 675 279 Operating Current 116 6.70 4.39 3.12 1.76 IDD 908 3.11 2.22 1.17 578 377 3.8 Min. Typ. 2.2 4.2 1.1 1.0
MTU8B54E/55E/56E/57E
6.2 ELECTRICAL CHARACTERISTICS of MTU8B55E/57E
Max. Units V V V V V 0.6 V uA uA mA mA mA mA mA mA mA uA uA uA mA mA mA mA uA mA mA mA mA uA uA Conditions I/O ports, Vdd=5V MCLR, Vdd=5V I/O ports, Vdd=5V MCLR, Vdd=5V I/O Ports, Vdd=4.5V, Ioh=-5.4mA, Iol=8.7mA in RC mode WDT Enable, Vdd=3.0V WDT Disable, Vdd=3.0V HFXTAL: 24MHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0v LFXTAL: 32kHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0V Vdd=2.4V Vdd=2.1V ** XTAL: 12MHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0V Vdd=2.4V XTAL: 4MHz, WDT Disable Vdd=6.4V Vdd=5.0V Vdd=4.0V Vdd=3.0V Vdd=2.1V **
Input Low Volatge
Output Voltage
Sleep Current
Revision 1.2
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MYSON TECHNOLOGY
Parameter Sym Min. Typ.
MTU8B54E/55E/56E/57E
Typ.
Units
Conditions Vdd=5V, RC mode, WDT Disable, These values include current through Rext
6.58 3.18 2.55 2.05 1.98 1.93 6.40 3.03 2.46 2.04 Operating Current IDD 1.97 1.93 5.90 2.79 2.34 2.02 1.97 1.93 5.48 2.60 2.28 2.02 1.98 1.93 ** Operating at Vdd=2.1V is for reference only.
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA C=301P C=101P C=20P C=3P
R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm R=900Ohm R=4.7kOhm R=10kOhm R=47kOhm R=100kOhm R=300kOhm
F=9.12MHz F=3.85MHz F=2.10MHz F=500kHz F=250kHz F=82.8Hz F=7.72MHz F=2.86MHz F=1.52MHz F=352kHz F=176kHz F=56.8kHz F=4.61MHz F=1.33MHz F=676kHz F=147kHz F=73.1kHz F=23.6kHz F=2.46MHz F=638kHz F=311kHz F=66.8kHz F=32.7kHz F=10.5kHz
Revision 1.2
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MYSON TECHNOLOGY
7.0 PACKAGE DIMENSION
MTU8B54E/55E/56E/57E
7.1 18 Pin PDIP 300mil for MTU8B54EN and MTU8B56EN
D
15o (4x)
E1
0.727
C TOP E-PIN INDENT 0.079 BOTTOM E-PIN INDENT 0.118
L
e
B1
B
D1
Dimension In Millemeters Symbols Min A A1 A2 B B1 C D D1 E E1 e L eB 0.13 0.36 1.27 0.20 22.71 0.43 7.62 6.40 3.18 8.38 Nom 3.30 0.46 1.52 0.25 22.96 0.56 6.50 2.54 Max 4.57 3.56 0.56 1.78 0.33 23.11 0.69 8.26 6.65 9.65 Min 0.005 0.014 0.050 0.008 0.894 0.017 0.300 0.252 0.125 0.330
A1 A2
A
Dimension In Inches Nom 0.130 0.018 0.060 0.010 0.904 0.022 0.256 0.100 Max 0.180 0.140 0.022 0.070 0.013 0.910 0.027 0.325 0.262 0.380
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eB
E
MYSON TECHNOLOGY
MTU8B54E/55E/56E/57E
7.2 18 Pin SOP for MTU8B54EP and MTU8B56EP
0.020x45o 7o (4x)
view "A"
E
H
D 7o (4x)
A2 A
view "A"
C
B
e
A1
L
Dimension In Millimeters Symbols Min A A1 A2 B C D E e H L 2.36 0.10 0.33 0.18 11.35 7.39 10.01 0.38 0o Nom 2.49 2.31 0.41 0.23 7.49 1.27 10.31 0.81 Max 2.64 0.30 0.51 0.28 11.76 7.59 10.64 1.27 80 Min 0.093 0.04 0.013 0.007 0.447 0.291 0.394 0.015 0o
Dimension In Inches Nom 0.098 0.091 0.016 0.009 0.295 0.050 0.406 0.032 Max 0.104 0.012 0.020 0.011 0.463 0.299 0.419 0.050 8o
Revision 1.2
- 17 -
24 October 2000
MYSON TECHNOLOGY
D
MTU8B54E/55E/56E/57E
7.3 28 Pin PDIP 300mil for MTU8B55EM and MTU8B57EM
15o (4x)
E1
1.000" PIN 1 INDENT
C
L
e
B1
B
B2 Dimension In Inches Min 0.015 0.0040 0.016 0.028 0.008 1.383 0.310 0.284 0.125 0.340 Nom 0.130 0.010 1.385 0.327 0.288 0.100 Max 0.180 0.140 0.065 0.023 0.044 0.013 1.395 0.330 0.296 0.380
Dimension In Millimeters Symbols Min A A1 A2 B B1 B2 C D E E1 e L eB 0.38 1.02 0.41 0.71 0.20 35.13 7.87 7.26 3.18 8.64 Nom 3.30 0.25 35.18 8.31 7.32 2.54 Max 4.57 3.56 1.65 0.58 1.12 0.33 35.43 8.38 7.52 9.65
Revision 1.2
- 18 -
A1 A2
A
24 October 2000
eB
E
MYSON TECHNOLOGY
D
MTU8B54E/55E/56E/57E
7.4 28 Pin PDIP 600mil for MTU8B55EN and MTU8B57EN
15o (4x)
E1
L
e
B1
B
Dimension In Millimeters Symbols Min A A1 A2 B B1 D E E1 e L eB 0.38 3.81 36.96 13.72 3.18 16.00 Nom 3.94 1.52 0.46 37.08 15.24 13.84 2.54 16.51 Max 5.59 4.06 37.34 13.97 17.02 Min 0.015 0.150 1.455 0.540 0.125 0.630
A1 A2
A
E
Dimension In Inches Nom 0.155 0.06 0.018 1.460 0.600 0.545 0.100 0.650 Max 0.220 0.160 1.470 0.550 0.670
Revision 1.2
- 19 -
24 October 2000
eB
MYSON TECHNOLOGY
MTU8B54E/55E/56E/57E
7.5 28 Pin SOP for MTU8B55EP and MTU8B57EP
0.020x45o 7o (4x)
eB
view "A"
E
D 7o (4x)
A2 A
view "A"
C
D1
B
A1
e
L
Dimension In Millimeters Symbols Min A A1 A2 B C D E e eB L 0.152 2.21 0.305 0.204 17.78 7.366 1.219 10.26 0.635 0o 0.356 Nom 2.488 2.336 0.406 0.254 17.91 7.493 1.270 10.42 4o 0.508 Max 2.743 2.464 0.508 0.304 18.42 7.62 1.321 10.57 80 Min 0.006 0.087 0.012 0.008 0.700 0.290 0.048 0.404 0.025 0o 0.014
Dimension In Inches Nom 0.098 0.091 0.016 0.010 0.705 0.295 0.050 0.410 4o 0.020 Max 0.108 0.097 0.020 0.012 0.725 0.300 0.052 0.416 8o -
D1
Revision 1.2
- 20 -
24 October 2000
MYSON TECHNOLOGY
8.0 PAD ASSIGNMENT
MTU8B54E/55E/56E/57E
8.1 Pad Assignmemt for MTU8B54E and MTU8B56E
TOCKI/SCL MCLR/Vpp PA3/SDA
18
17
16
15
14
13
12
11
10
Pad of MTU8B54E/56E
Chip size : 1710um x 1760um Pad size : 110um x 110um 1
PB0
2
PB1
3
PB2
4
PB3
5
PB4
6
PB5
7
PB6
8
PB7
Pad No. 1 2 3 4 5 6 7 8 9
Pad PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Vdd
X 145.45 320.95 496.45 671.95 847.45 1022.95 1198.45 1373.95 1557.45
Y 153.05 153.05 153.05 153.05 153.05 153.05 153.05 153.05 153.05
Pad No. 10 11 12 13 14 15 16 17 18
Pad OSCO OSCI PA0 PA1 PA2 PA3/SDA TOCKI/SCL MCLR/Vpp Vss
Vdd
OSCO
OSCI
PA2
PA1
Vss
PA0
9
X 1598.95 1264.95 1098.45 922.95 747.45 571.95 424.90 249.20 124.20
Y 1606.95 1606.95 1606.95 1606.95 1606.95 1606.95 1606.95 1606.95 1606.95
Revision 1.2
- 21 -
24 October 2000
MYSON TECHNOLOGY
MCLRB/Vpp T0CKI/SCL
MTU8B54E/55E/56E/57E
8.2 Pad Assignment for MTU8B55E and MTU8B57E
OSCO
OSCI
20 Vss PA0 PA1 PA2 PA3 PB0 21
PB1
19
18
17
16
15
14 12 11 10
PC7
Vdd
PC6 PC5 PC4 PC3 PC2 PC1
Pad of MTU8B55E/57E
Chip size : 2201um x 1822um Pad size : 110um x 110um 1 2
PB2
3
PB3
4
PB4
5
PB5
6
PB6
7
PB7
8
PC0
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13
Pad PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5
X 217.01 476.09 720.67 979.75 1224.33 1483.41 1727.99 1987.07 2117.01 2117.01 2117.01 2117.01 2117.01
Y 93.20 93.20 93.20 93.20 93.20 93.20 93.20 93.20 361.40 620.48 865.06 1124.14 1386.72
Pad No. 14 15 16 17 18 19 20 21 22 23 24 25 26
Pad PC6 PC7 OSCO OSCI MCLR/Vpp TOCKI/SCL Vdd Vss PA0 PA1 PA2 PA3/SDA PB0
9
13
22 23 24 25 26
X 2117.01 1830.89 1595.29 1210.68 863.95 603.04 344.41 101.98 93.21 93.21 93.21 93.21 93.21
Y 1627.80 1738.75 1733.20 1733.20 1738.79 1738.75 1738.75 1644.97 1372.18 1127.60 868.52 623.94 364.86
Revision 1.2
- 22 -
24 October 2000
MYSON TECHNOLOGY
9.0 Order Information
Type 18pins 28pins 18pins 28pins 300mil PDIP MTU8B54EN MTU8B55EM MTU8B56EN MTU8B57EM 600mil PDIP MTU8B55EN MTU8B57EN
MTU8B54E/55E/56E/57E
300mil SOP MTU8B54EP MTU8B55EP MTU8B56EP MTU8B57EP
Die Form MTU8B54E MTU8B55E MTU8B56E MTU8B57E
Revision 1.2
- 23 -
24 October 2000

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